In the integrated circuit (IC) industry, bus protocols are used to communicate software instructions and data between a CPU core and external memory devices. Currently, microprocessors and microcontroller cores are capable of operating at frequencies in the range of hundreds of megahertz (e.g., 300 MHz). However, high performance bus operation is typically constrained to operational frequencies on the order of tens of megahertz (e.g., about 50 MHz). Therefore, the bus protocol used in a data processing system is typically a bottleneck to further improvement of system performance. In order to improve upon this performance bottleneck, whereby overall computer system performance can be improved, the simplifying of the bus protocol has become a goal in the integrated circuit industry. The simplification of the bus protocol reduces speed critical paths, reduces timing overhead, and generally speeds bus operation.
In addition, it is desirable in the integrated circuit industry to manufacture microcontrollers having a simplified cored design whereby less silicon surface area is used, thereby reducing manufacturing costs, and whereby power consumption can be reduced for longer battery life. In summary, many current microprocessor and microcontroller designs are removing control signals and timing complexity from bus protocols in order to improve upon bus system performance while simultaneously removing logic from CPU cores to enable more compact and efficient CPU EBB circuit area.
These two goals of simplifying the microprocessor bus protocol and reducing the amount of circuitry in a semiconductor CPU core create problems in current microcontroller design. For example, conventional bus transfer termination signals in the bus protocol are no longer available to terminate bus cycles when the bus is in a locked state. Therefore, this simplification process complicates bus lock recovery and may either complicate watch dog design or render current watch dog designs nonfunctional in the more modem (i.e., simplified) bus protocols.
In prior art watchdog and bus lock recovery systems, a first timer is a watch-dog timer which is used to control the occurrences of software interrupts within the data processing system. These software interrupts generated from a first set of time out events in the first timer are used to monitor software execution flow whereby the software interrupts can detect when software execution is locked in an improper execution path while the bus may still be in a proper unlocked functional mode. A second timer keeps track of second time periods and generates a second set of time out events that are used to terminate bus cycles when the bus hardware/protocol itself enters a locked bus state. In other words, the CPU may initiate a bus cycle on an external bus whereby this bus cycle never properly terminates due to some problem with the bus itself or peripherals attached to the CPU. When this locked state occurs, the second timer will time-out, forcing the bus to perform a termination operation whereby some form of functional bus operation can be eventually restored to the system. However, due to the process of simplifying bus protocols and shrinking a physical size of the CPU, two physical timers are no longer feasible for use in microcontroller designs to support these two separate functions.
Therefore, a need exists in the industry for a new microcontroller design which can support both timed bus cycle termination functions and software watchdog interrupts for simplified bus protocol while simultaneously achieving the advantageous result of reducing a complexity of the CPU core design and CPU bus protocol.